1. Field of the Invention
The present invention relates to timing-driven layout for a circuit. More particularly, the invention relates to a method of performing timing-driven layout of a circuit that uses “fan-out capacitance limitation values” of the respective functional blocks of a circuit to find the timing-error blocks in these functional blocks, which is preferably used for layout of a Large-Scale Integrated circuit (LSI).
2. Description of the Related Art
In recent years, with the rapid increase in integration scale and operation speed of LSIs, it has become extremely difficult to decrease manually the number of timing errors in a LSI layout obtained by its placement and routing processes toward zero as desired. This means that it has become extremely difficult to realize manually the desired timing error convergence. To solve this problem, timing-driven layout methods have ever been developed to make it possible to automate the timing error convergence in the layout design operation.
Generally, “layout design” for LSIs means the design to form and allocate desired devices and their wiring lines on a chip, which has a hierarchical structure. Specifically, the “layout design” includes typically the “partitioning”, “floor planning”, “placement”, and “routing” processes. The usual layout design is performed to minimize the chip area (i.e., maximize the integration level) and maximize the wiring efficiency. Unlike this, the “timing-driven layout design” is performed not only to minimize the chip area (i.e., maximize the integration level) and maximize the wiring efficiency but also to satisfy the timing constraints given.
“Partitioning”, which is performed to decrease the complexity of overall layout, is a design process to group required gates and/or cells for a specific LSI into functional blocks to thereby divide the overall layout into “in-block layout” and “inter-block layout”. This facilitates the subsequent design processes.
“Floor planning” is a design process to determine the schematic layout (i.e., schematic “in-block layout” and “inter-block layout”) of the respective functional blocks formed through the partitioning process and the schematic layout of the wiring lines thereof. Due to “floor planning”, the framework or skeletal structure of the LSI is determined.
“Placement” is a design process to determine the location and shape of the respective functional blocks.
“Routing” is a design process to determine the route or path of the wiring lines in and among the respective functional blocks.
FIG. 1 is a flowchart showing a typical example of the prior-art timing-driven layout methods of this type, which uses a timing constraint file that identifies the locations causing timing errors.
As shown in FIG. 1, in the step S101, initial placement of the functional blocks is performed based on the initial placement data. The initial placement data of the blocks are derived from the floor-planning data generated by a known method before the step S101. The routing process for wiring lines of the blocks is not performed at this stage.
In the step S102, a timing constraint file is formed by the timing constraint data generated from the initial placement data.
In the step S103, approximate propagation delay for the initial placement data is calculated.
In the step S104, it is judged whether the timing error convergence for the approximate propagation delay thus calculated is acceptable or not. If the judgment result in the step S104 is “No”, the circuit configuration of the blocks and the placement thereof are corrected in the step S105 and then, the flow is returned to the step S102, repeating the steps S102 to S104. If the judgment result in the step S104 is “Yes”, routing of the wiring lines for the blocks is performed in the step S106 and then, the wiring lines thus routed are corrected and adjusted according to the timing constraint data. The timing constraint data are generated from the timing constraint file.
In the step S10, it in judged whether the timing error convergence for the placement blocks and the routed wiring lines thus corrected and adjusted is acceptable or not. If the judgment result in the step S108 is “No”, the flow is returned to the step S102, repeating the steps S102 to S104. If the result of judgment in the step S108 is “Yes”, the flow is completed.
With the prior-art timing-driven layout method of FIG. 1, the timing constraint file (i.e., the timing constraint data) used to find the timing-error-causing locations is necessary. Thus, there is a problem that the identification behavior for the timing-error-causing locations and the content to be corrected or adjusted are largely affected by how the description of the timing constraint data is described.
Moreover, with the prior-art method of FIG. 1, wiring lengths are estimated or predicted to calculate the estimated propagation delay values and then, the timing-error-causing locations and the content for optimization are determined according to the estimated propagation delay values. Thus, some error or difference occurs between the actual wiring-induced delay values and the estimated wiring-induced delay values and as a result, there is another problem that accurate optimization is unable to be conducted.
Additionally, to eliminate the error between the actual and estimated wiring-induced delay values, the wiring lines needs to be changed or corrected after the placement and touting processes are completed. Therefore, the estimated wiring length differs from the actual wiring length and as a result, there is a possibility that timing error is not sufficiently converged as desired.